ISC specimen Computer Science paper , Group A (part II)

Q 4.a) Given the Boolean function F(P,Q,R,S)= Σ(0,1,3,4,5,6,7,9,10,11,13,15)
Using Karnaugh’ map to reduce the function F, using SOP form. Draw the logic gate diagram
of the reduced SOP form. You may use gates with more than 2 inputs. Assume that the variables and their complements are available as inputs.
                                                                                                                                              [ 4 + 1 = 5 ]

Sol. The Karnaugh' map for the given expression is as follows

Quad 1 (m₀ +m₁ +m₄ +m₅ )= P'R'

Quad 2 (m₄  +   m₅   +  m₆ +   m₇  )= P'Q

Octet 1 (  m₁ + m₃  +   m₅  + m₇  +m₉  +m₁₁  +m₁₃  +m₁₅  )= S
 Diad 1 (m₁₀  +   m₁₁ )=PQ'R 

   

                                                                                                                                                                                   The reduced expression as per Karnaugh' map = S+P'R'+P'Q+PQ'R

(N.B. From the octet you get S , from the quatret shown in light grey in the figure you get P'R' from the second quatret shown in darker shade you will get P'Q and finally from the diad you get PQ'R)

The logic diagram of the reduced sum of products is as follows,

Q 4b)  Given the Boolean function F(P,Q,R,S)= π(3,8,10,12,13,14,15)

Using Karnaugh’ map to reduce the function F, using POS form. Draw the logic gate diagram of the reduced POS form. You may use gates with more than 2 inputs. Assume that the

variables and their complements are available as inputs.                                              4+1=5                                               

 Sol: The Karnaugh' map of the given Boolean function is as follows

Quad 1 (M₁₂M₁₃M₁₄M₁₅ )= (P+Q)

Diad 1 (M₈M₁₂)=(P+R'+S')

Diad 2 (M₁₀ M₁₄ ) =( P+R+S')

M₃  =  (P'+Q'+R+S)
 

The reduced expression based on the Karnaugh map is as follows 

 

(P'+Q'+R+S)(P+Q)(P+R'+S')(P+R+S')

The logic gate diagram of the above is given as follows 

Q 5) The main safe in the nationalizes bank can be opened by means of a unique password consisting of

three parts. Different parts f the password are held by the chairman, Regional Manager, Bank

Manager and Head Cashier of the bank, respectively.

In order to open the safe any one of the following conditions must be satisfied:

The password of the chairman, together with passwords of any two other officials, must be entered.

OR

The password of all three bank officials, excluding the chairman, must be entered.

The inputs are:

INPUTS

A Denotes the chairman’s password

B Denotes the Regional Manager’s password

C Denotes the Bank Manager’s password

D Denotes the Head Cashier’s password

Output

X Denotes the safe can be opened[ 1 indicates YES ad 0 indicates NO in all cases]

a) Draw the truth table for the inputs and outputs given above and write the SOP expression

for X(A,B,C,D)..

b) Reduce X(A,B,C,D) using Karnaugh’s map, if possible.

Draw the logic gate diagram for the reduced SOP expression for X(A,B,C,D) using AND and

OR gates. You may use gates with two or more inputs. Assume that the variable and their

complements are available as inputs.

                                                                                                                                         [ 5 x 2 = 10]

Sol a) : The truth table of the above problem is as follows,                                                                    

The Sum of Products expression based on the above truth table  is                                                            

F(A,B,C,D)=Σ(7,11,13,14,15)

b)  The Karnaugh's map of the above sum of products is as follows ,                                                              

                                           
Diad 1 (m₇  + m₁₅  ) = BCD
Diad 2 (m₁₃  +m₁₅  )= ABD
Diad 3 (m₁₅  +m₁₄  )= ABC
Diad 4 (m₁₁   + m₁₅  )= ACD
 
 The reduced expression according to the Karnaugh's map is  
                    ABD+ABC+BCD+ACD

The logic gate diagram for the above expression is as given below.

                                                  

[NB: It is always better to attempt questions like above. the Karnaugh's map for this question is much easier. You may initially find the question too lengthy and decide to opt this out , but please I would rather suggest you to go through it at least once .  It's a no-brainer and just a set of instructions to create a truth table based on the variables and the rest is just like question 4 . Only thing you do not have to draw and solve the Karnaugh's map twice if you attempt Q4. Please let me know if you want me to do a tutorial on K-map because you have to compulsorily attempt this in your examination.]

Q 6. a) Draw the truth table and logic circuit diagram for a Decimal to Binary Encoder. [ 5 ]

b) Given F(X,Y,Z)=Σ(1,3,7) Verify : F(X,Y,Z)= π(0,2,4,5,6) [ 2 ]

c) Simplify the following expression by using Boolean laws. Show the working and also

mention the laws used: X’Y’Z’ + XYZ’ +XY’Z’ + X’YZ’ [ 3 ]

Sol. a)      The truth table for a Decimal to Binary encoder is as follows

The circuit diagram for the same is as follows                                                                    

b) F(X,Y,Z)=Σ(1,3,7)

F'(X,Y,Z)=(Σ(1,3,7))'

                    = Σ(0,2,4,5,6)

                                          =( m₀+m₂+m₄+m₅+m₆ )'

                                          = m₀´m₂´m₄´m₅´m₆´ 

                                    =  M₀M₂M₄M₅M₆

                              ₌ π(0,2,4,5,6)

c)X'Y'Z'+XYZ'+XY'Z'+X'YZ'

=X'Y'Z'+X'YZ'+XYZ'+XY'Z'

=X'Z'(Y+Y')+XZ'(Y+Y')

                            =X'Z'.1+XZ'.1  (By complement)          

 =Z'(X'+X)                    

                            =Z'.1 (By complement)                 

=Z'     

Q 6)       a) Define cardinal form of an expression and canonical form of an expression. Give an example for each  [3]

b) Which gate is equivalent to : (NOR) OR (XOR) [ 3 ]

c) Define a Half Adder. Draw the truth table and logic diagram of a half adder. [ 4 ]

a) In cardinal form of expression terms that form a function may contain one , two or any number of literals.There are two types of cardinal forms - sum of products and product of sum . An example for each type is given as 

i) F(A,B,C) =AB'C'+ABC'+A'B'C (Sum of products form)

ii) F(A,B,C)=(A+B'+C')(A+B+C')(A'+B'+C)  (Product of sum form)

Boolean expressions that are expressed as sum of min terms or product of max terms are said to be in canonical form .  An example  of   each  is   given                                                                                    i) F(A,B,C)= Σ(0,1,3,4,5)  (Sum of min terms)

ii) F(A,B,C)= π(2,6,7)  (Product of max terms)

b) A NOR gate is algebraically implemented as A'B'

An XOR gate is implemented as A'B+AB'

The given expression is algebraically implemented as = (A'B') + (A'B+AB')

=A'B'+A'B+AB'

=A'(B'+B)+AB'

=A'+AB'

Now let us consider truth table of the above expression 

                         Therefore from the above truth table it is evident that the given combination of gates works as a nand gate which gives a zero output when all the inputs are positive.

c)  Half Adder is an example of a simple functional digital circuit built from two logic gates . The half adder adds two one-bit binary numbers (A, B) .  The output is the sum of two bits (S) and the carry (C). The truth table of the half adder is as follows 

                            The logic diagram of half adder is given below,